![]() architecture fixupstruc of fixup is signal FSEL: STDLOGICVECTOR(15 downto 0) - Fixup. You will have to compile in VHDL-2008 mode for this to work. Table XCvhd-6 Structural VHDL architecture for left-shift fix-ups. This will automatically include all the relevant signals. if you don't want to worry about signals missing from the sensitivity list, you can use the VHDL-2008 method process(all). ![]() And if you type if rst='1' then you never have to follow by elsif rst='0': of course rst='0' if it's not '1'.įinally, don't use the STD_LOGIC_unsigned package. signal result_int : unsigned(result'range) := (others => '0') In this case you can avoid the variables by detecting the zero and n-flag outside of the process statement. Try to avoid the use of variables anyhow. If alu_mode(2 downto 0)="111" you first set both flags, but immediately overwrite them if (temp = x"0000" ) or if (temp(15) = '1' ). Secondly, your flag setting is screwed up. This way it will no longer be a problem that signals are missing from the sensitivity list. Or -preferably- a synchronous process with synchronous reset main_proc: process(clk) ![]() You should either have a synchronous process with an asynchronous reset main_proc: process(rst, clk) First of all, even though you have a clock input port, your design is asynchronous. When "110" => temp := std_logic_vector(shift_right((unsigned(rd_data1)),to_integer(unsigned(shift)))) When "101" => temp := std_logic_vector(shift_left(unsigned(rd_data1),to_integer(unsigned(shift)))) When "100" => temp := rd_data1 NAND rd_data2 Variable m_temp : std_logic_vector(31 downto 0) ![]() Variable temp : STD_LOGIC_VECTOR(15 downto 0):=X"0000" Shift : in std_logic_vector (3 downto 0) Result : out STD_LOGIC_VECTOR (15 downto 0) Rd_data2 : in STD_LOGIC_VECTOR (15 downto 0) Īlu_mode : in STD_LOGIC_VECTOR (2 downto 0) Port ( rd_data1 : in STD_LOGIC_VECTOR (15 downto 0) Uncomment the following library declaration if instantiating arithmetic functions with Signed or Unsigned values Uncomment the following library declaration if using I can't figure out where I've gone wrong. However I've been forced to change that to a 4 bit std_logic_vector called 'shift' and now it won't shift anymore. VHDL Part 19 : Counter with integer to std_logic_v.I had this alu working with the shift left/right function when and the shift amount was being sent in on rd_data2, a 16 bit std_logic_vector.VHDL Part 21 : Counter with Seven-Segment Display.VHDL Part 27 : Comparator using if-then-else.VHDL Part 28 : Comparator using when-else statement.I had dropped the MSB for shift-left or the LSB for shift-right. Please take note of the boundaries of shReg_in in the code. Unlike the previous post where I just used fixed bit '1' (or '0') to push the bits to the right, here I used an external input (sh_in) that will shift the bit vectors (shReg_in) either to the right or to the left. On the rising edge of the clock, the code performs the necessary shift. This is a good practice especially if the length of the bit vector is very long. the statement below is for shift-right register for shift-left register, replace the statement below with: shReg _out '0') to fill the bit vector up with logic 0s. ShReg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0)) ShReg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0) Generic ( regCount : natural := n) - replace n with 4, 5, 8, etc. I used the concatenation operator to push the bits to the right and drop the LSB. I replaced the n in the generic declaration with the number I want. I found another way of implementing an n-bit shift-right/left register.
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